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LT1010 Fast 150mA Power Buffer
FEATURES

DESCRIPTIO
20MHz Bandwidth 75V/s Slew Rate Drives 10V into 75 5mA Quiescent Current Drives Capacitive Loads > 1F Current and Thermal Limit Operates from Single Supply 4.5V Very Low Distortion Operation Available in 8-Pin miniDIP, Plastic TO-220 and Tiny 3mm x 3mm x 0.75mm 8-Pin DFN Packages
The LT(R)1010 is a fast, unity-gain buffer that can increase the output capability of existing IC op amps by more than an order of magnitude. This easy-to-use part makes fast amplifiers less sensitive to capacitive loading and reduces thermal feedback in precision DC amplifiers. Designed to be incorporated within the feedback loop, the buffer can isolate almost any reactive load. Speed can be improved with a single external resistor. Internal operating currents are essentially unaffected by the supply voltage range. Single supply operation is also practical. This monolithic IC is supplied in 8-pin miniDIP, plastic TO-220 and 8-pin DFN packages. The low thermal resistance power package is an aid in reducing operating junction temperatures.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

Boost Op Amp Output Isolate Capacitive Loads Drive Long Cables Audio Amplifiers Video Amplifiers Power Small Motors Operational Power Supply FET Driver
TYPICAL APPLICATIO
V+ 18V
Very Low Distortion Buffered Preamplifier
0.4
C2 22pF V+ 6 R4 10k V+ R6 100 IN LT1010CT V
R7 50
HARMONIC DISTORTION (%)
0.3
R1 1k
3 C1 22pF
+ -
7
R2 1M
LT1056CN8 2 R3 1k 4
BOOST OUT
R8 100 OUTPUT
-
NOTE 1: ALL RESISTORS 1% METAL FILM NOTE 2: SUPPLIES WELL BYPASSED AND LOW ZO V+ -18V
LM334 ISET = 2mA V -
RSET 33.2 1%
1010 TA01
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VOUT = 10VP-P RL = 400 0.2 0.1 0 10 100 1k 10k FREQUENCY (Hz) 100k
1010 TA02
U
U
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1
LT1010
ABSOLUTE
(Note 1)
AXI U
RATI GS
PRECO DITIO I G
100% Thermal Limit Burn In-LT1010CT
Total Supply Voltage .............................................. 22V Continuous Output Current .............................. 150mA Input Current (Note 3) ....................................... 40mA Operating Junction Temperature Range LT1010C ............................................... 0C to 100C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
PACKAGE/ORDER I FOR ATIO
TOP VIEW V+ 1 BIAS 2 OUT 3 NC 4 9 8 7 6 5 INPUT NC V
-
TOP VIEW V+ 1 BIAS 2 OUT 3 NC 4
DD PACKAGE 8-LEAD (3mm x 3mm) PLASTIC DFN
8 INPUT 7 NC 6 V- 5 NC N8 PACKAGE 8-LEAD PDIP
V-
NC
TJMAX = 100C, JC = 3C/W, JA = 40C/W EXPOSED PAD (PIN 9) V- CAN BE SOLDERED TO PCB TO REDUCE THERMAL RESISTANCE (NOTE 7)
TJMAX = 100C, JC = 45C/W, JA = 100C/W
ORDER PART NUMBER LT1010CDD
DD PART MARKING LBWZ
ORDER PART NUMBER LT1010CN8
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VOS PARAMETER Output Offset Voltage
The indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (See Note 4. Typical values in curves.)
CONDITIONS (Note 4) (Note 4)
VS = 15V, VIN = 0V IB Input Bias Current IOUT = 0mA IOUT 150mA

AV ROUT
Large-Signal Voltage Gain Output Resistance IOUT = 1mA IOUT = 150mA
Slew Rate
VS = 15V, VIN = 10V, VOUT = 8V, RL = 100
2
UU
U
U
U
W
WW U
W
FRONT VIEW 5 4 3 2 1 T PACKAGE 5-LEAD PLASTIC TO-220 OUTPUT BIAS V - (TAB) V+ INPUT
TJMAX = 125C, JC = 3C/W, JA = 50C/W
ORDER PART NUMBER LT1010CT
MIN 0 -20 20 0 0 0 0.995 5 5 75
TYP
MAX 150 220 100 250 500 800 1.00 10 10 12
UNITS mV mV mV A A A V/V V/s
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LT1010
ELECTRICAL CHARACTERISTICS
SYMBOL VSOS+ VSOS- RSAT VBIAS IS PARAMETER Positive Saturation Offset Negative Saturation Offset Saturation Resistance Bias Terminal Voltage Supply Current
The indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (See Note 4. Typical values in curves.)
CONDITIONS (Note 4) IOUT = 0 (Note 5)
MIN
TYP
MAX 1.0 1.1 0.2 0.3 22 28
UNITS V V V V mV mV mA mA
IOUT = 0 (Note 5)
IOUT = 150mA (Note 5)
RBIAS = 20 (Note 6)
700 560
840 880 9 10
IOUT = 0, IBIAS = 0
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: For case temperatures above 25C, dissipation must be derated based on a thermal resistance of 25C/W for the T package, 130C/W for the N8 package and 40C/W for the DD package for ambient temperatures above 25C. See Applications Information. Note 3: In current limit or thermal limit, input current increases sharply with input-output differentials greater than 8V; so input current must be limited. Input current also rises rapidly for input voltages 8V above V + or 0.5V below V -. Note 4: Specifications apply for 4.5V VS 40V, V - + 0.5V VIN V + - 1.5V and IOUT = 0, unless otherwise stated. Temperature range is 0C TJ 100C, TC 100C.
Note 5: The output saturation characteristics are measured with 100mV output clipping. See Applications Information for determining available output swing and input drive requirements for a given load. Note 6: The output stage quiescent current can be increased by connecting a resistor between the BIAS pin and V +. The increase is equal to the bias terminal voltage divided by this resistance. Note 7: Thermal resistance varies depending upon the amount of PC board metal attached to the pin (Pin 9) of the device. JA is specified for a certain amount of 1oz copper metal trace connecting to Pin 9 as described in the thermal resistance tables in the Applications Information section.
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3
LT1010 TYPICAL PERFOR A CE CHARACTERISTICS
Bandwidth
50 RL = 200 40
PHASE LAG (DEGREES) PHASE LAG (DEGREES)
FREQUENCY (MHz)
30
RL = 50
20 VIN = 100mVP-P CL 100pF AV = -3dB TJ = 25C 0 30 20 10 QUIESCENT CURRENT (mA) 40
1010 G01
10
0
Small-Step Response
150 100
OUTPUT IMPEDANCE ()
RL = 100 TJ = 25C
VOLTAGE CHANGE (mV)
VOLTAGE GAIN (dB)
50 INPUT 0 -50 OUTPUT
-100 -150
1
0
10 TIME (ns)
20
Slew Response
20 15 400
5 0 -5 -10 RBIAS = 20 -15 -20 -50 0 50 150 100 TIME (ns) IBIAS = 0
VS = 15V RL = 100 TJ = 25C f 1MHz NEGATIVE
RL = 100 200 RL = 50
SUPPLY CURRENT (mA)
OUTPUT VOLTAGE (V)
10
POSITIVE
SLEW RATE (V/s)
4
UW
1010 G04
Phase Lag
50 50
Phase Lag
20 RL = 50 RL = 200 10 CL = 100pF RS = 50 IBIAS = 0 TJ = 25C 2 5 10 FREQUENCY (MHz) 20
1010 G02
20 RL = 50 RL = 200
10 CL = 100pF RS = 50 RBIAS = 20 TJ = 25C 2 5 10 FREQUENCY (MHz) 20
1010 G03
5
5
Output Impedance
100 IBIAS = 0 TJ = 25C
Capacitive Loading
10 RS = 50 IBIAS = 0 TJ = 25C
0 3nF 100pF
10
-10 0.1F
30
0.1
1 10 FREQUENCY (MHz)
100
1010 G05
-20 0.1 1 10 FREQUENCY (MHz) 100
1010 G06
Negative Slew Rate
VS = 15V 0 VIN -10V RL = 200 80
Supply Current
VS = 15V VIN = 10V IL = 0 TC = 25C
300
60
40
100
20
200
250
1010 G07
0
0 0 20 10 30 QUIESCENT CURRENT (mA) 40
1010 G08
0
1
2 3 FREQUENCY (MHz)
4
5
1010 G09
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LT1010 TYPICAL PERFOR A CE CHARACTERISTICS
Output Offset Voltage
200 VIN = 0
OFFSET VOLTAGE (mV)
BIAS CURRENT (A)
BIAS CURRENT (A)
150 V + = 38V V - = -2V V + = 2V V - = -38V
100
50
0 -50
0
100 TEMPERATURE (C)
50
Voltage Gain
1.000 IOUT = 0
12 10
OUTPUT RESISTANCE ()
NOISE VOLTAGE (nV/Hz)
VS = 40V 0.999
GAIN (V/V)
VS = 4.5V 0.998
0.997 -50
0
100 50 TEMPERATURE (C)
Positive Saturation Voltage
4 4
SATURATION VOLTAGE (V)
SATURATION VOLTAGE (V)
3
3
SUPPLY CURRENT (mA)
IL = 150mA
2 IL = 50mA 1 IL = 5mA
0 -50
0
100 TEMPERATURE (C)
50
UW
1010 G10 1010 G16
Input Bias Current
200 VIN = 0
200
Input Bias Current
VS = 15V RL = 75
150 V 100 V + = 38V - = -2V
150 TJ = 125C TJ = 25C 100 TJ = -55C 50
50
V + = 2V V - = -38V
150
0 -50
0
100 TEMPERATURE (C)
50
150
1010 G10
0 -150
-100
-50 50 100 0 OUTPUT CURRENT (mA)
150
1010 G12
Output Resistance
IOUT 150mA 200
Output Noise Voltage
TJ = 25C
150
8 6 4 2 0 -50
100
RS = 1k 50 RS = 50 0 10 100 1k FREQUENCY (Hz) 10k
1010 G15
150
1010 G13
0
100 50 TEMPERATURE (C)
150
1010 G14
Negative Saturation Voltage
7
Supply Current
VIN = 0 IOUT = 0 IBIAS = 0
IL = -150mA
TJ = -55C
6 TJ = 25C 5
2 IL = -50mA 1 IL = -5mA
4
TJ = 125C
150
0 -50
0
100 TEMPERATURE (C)
50
150
1010 G16
3
0
20 10 30 TOTAL SUPPLY VOLTAGE (V)
40
1010 G18
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5
LT1010 TYPICAL PERFOR A CE CHARACTERISTICS
Bias Terminal Voltage
1.0 VS = 20V
BIAS TERMINAL VOLTAGE (V)
HARMONIC DISTORTION (%)
0.3
HARMONIC DISTORTION (%)
0.9
0.8 RBIAS = 20
RBIAS = 100
0.7
0.6
0.5 -50
0
100 50 TEMPERATURE (C)
Shorted Input Characteristics
50 VS = 15V VOUT = 0 TJ = 25C
PEAK POWER (W)
10
6 TO-220
OUTPUT CURRENT (A)
INUPT CURRENT (mA)
25
0
-25
-50 -15
-10
5 0 INPUT VOLTAGE (V)
-5
6
UW
1010 G19
Total Harmonic Distortion
0.4 RL = 50 f = 10kHz VS = 15V TC = 25C
0.8
Total Harmonic Distortion
IBIAS = 0 VS = 15V VOUT = 10V TC = 25C
0.6
0.2 IBIAS = 0 0.1 RBIAS = 50
0.4 RL = 50 0.2 RL = 100
150
0 0.1
0
1 10 OUTPUT VOLTAGE (VP-P)
100
1010 G20
1
10 100 FREQUENCY (kHz)
1000
1010 G21
Peak Power Capability
TC = 85C
Peak Output Current
0.5 VS = 15V VOUT = 0 SINK 0.3 SOURCE 0.2
8
0.4
4
2
0.1
0
10
15
1010 G22
1
10 PULSE WIDTH (ms)
100
1010 G23
0 -50
0
100 50 TEMPERATURE (C)
150
1010 G24
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LT1010
APPLICATIO S I FOR ATIO
General
These notes briefly describe the LT1010 and how it is used; a detailed explanation is given elsewhere1. Emphasis here will be on practical suggestions that have resulted from working extensively with the part over a wide range of conditions. A number of applications are also outlined that demonstrate the usefulness of the buffer beyond that of driving a heavy load. Design Concept The schematic below describes the basic elements of the buffer design. The op amp drives the output sink transistor, Q3, such that the collector current of the output follower, Q2, never drops below the quiescent value (determined by I1 and the area ratio of D1 and D2). As a result, the high frequency response is essentially that of a simple follower even when Q3 is supplying the load current. The internal feedback loop is isolated from the effects of capacitive loading by a small resistor in the output lead.
V+ D1 D2 BIAS I2
Q2 Q1
A1
INPUT OUTPUT
R1
I1
Q3 V-
1010 AI01
The scheme is not perfect in that the rate of rise of sink current is noticeably less than for source current. This can be mitigated by connecting a resistor between the bias terminal and V +, raising quiescent current. A feature of the final design is that the output resistance is largely independent of the follower quiescent current or the output load current. The output will also swing to the negative rail, which is particularly useful with single supply operation. Equivalent Circuit Below 1MHz, the LT1010 is quite accurately represented by the equivalent circuit shown here for both small- and large-signal operation. The internal element, A1, is an
U
idealized buffer with the unloaded gain specified for the LT1010. Otherwise, it has zero offset voltage, bias current and output resistance. Its output also saturates to the internal supply terminals2.
V+ VSOS+ R VOS INPUT IB
W
UU
+
+
ROUT A1 OUTPUT
R
R = RSAT - ROUT
VSOS- V-
1010 AI02
Loaded voltage gain can be determined from the unloaded gain, AV, the output resistance, ROUT, and the load resistance, RL, using:
A VL = A VRL ROUT + RL
Maximum positive output swing is given by:
VOUT =
+
( V + - VSOS+ )RL RSAT + RL
-
The input swing required for this output is:
R + VIN = VOUT + 1 + OUT - VOS + VOS RL
where VOS is the 100mV clipping specified for the saturation measurements. Negative output swing and input drive requirements are similarly determined. Supply Bypass The buffer is no more sensitive to supply bypassing than slower op amps as far as stability is concerned. The 0.1F disc ceramic capacitors usually recommended for op amps are certainly adequate for low frequency work. As always, keeping the capacitor leads short and using a
1R. J. Widlar, "Unique IC Buffer Enhances Op Amp Designs; Tames Fast Amplifiers,"
Linear Technology Corp. TP-1, April, 1984. 2See electrical characteristics section for guaranteed limits.
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LT1010
APPLICATIO S I FOR ATIO
ground plane is prudent, especially when operating at high frequencies. The buffer slew rate can be reduced by inadequate supply bypass. With output current changes much above 100mA/s, using 10F solid tantalum capacitors on both supplies is good practice, although bypassing from the positive to the negative supply may suffice. When used in conjunction with an op amp and heavily loaded (resistive or capacitive), the buffer can couple into supply leads common to the op amp causing stability problems with the overall loop and extended settling time. Adequate bypassing can usually be provided by 10F solid tantalum capacitors. Alternately, smaller capacitors could be used with decoupling resistors. Sometimes the op amp has much better high frequency rejection on one supply, so bypass requirements are less on this supply. Power Dissipation In many applications the LT1010 will require heat sinking. Thermal resistance, junction to still air is 100C/W for the TO-220 package and 130C/W for the miniDIP package. Circulating air, a heat sink or mounting the package to a printed circuit board will reduce thermal resistance. In DC circuits, buffer dissipation is easily computed. In AC circuits, signal waveshape and the nature of the load determine dissipation. Peak dissipation can be several times average with reactive loads. It is particularly important to determine dissipation when driving large load capacitance. With AC loading, power is divided between the two output transistors. This reduces the effective thermal resistance, junction to case to 15C/W for the TO-220 package as long as the peak rating of neither output transistor is exceeded. The typical curves indicate the peak dissipation capabilities of one output transistor. Overload Protection The LT1010 has both instantaneous current limit and thermal overload protection. Foldback current limiting has not been used, enabling the buffer to drive complex loads
8
U
without limiting. Because of this, it is capable of power dissipation in excess of its continuous ratings. Normally, thermal overload protection will limit dissipation and prevent damage. However, with more than 30V across the conducting output transistor, thermal limiting is not quick enough to ensure protection in current limit. The thermal protection is effective with 40V across the conducting output transistor as long as the load current is otherwise limited to 150mA. Drive Impedance When driving capacitive loads, the LT1010 likes to be driven from a low source impedance at high frequencies. Certain low power op amps (e.g., the LM10) are marginal in this respect. Some care may be required to avoid oscillations, especially at low temperatures. Bypassing the buffer input with more than 200pF will solve the problem. Raising the operating current also works. Parallel Operation Parallel operation provides reduced output impedance, more drive capability and increased frequency response under load. Any number of buffers can be directly paralleled as long as the increased dissipation in individual units caused by mismatches of output resistance and offset voltage is taken into account. When the inputs and outputs of two buffers are connected together, a current, IOUT, flows between the outputs:
IOUT = VOS1 - VOS2 ROUT1 + ROUT2
W
UU
where VOS and ROUT are the offset voltage and output resistance of the respective buffers. Normally, the negative supply current of one unit will increase and the other decrease, with the positive supply current staying the same. The worst-case (VIN V +) increase in standby dissipation can be assumed to be IOUTVT, where VT is the total supply voltage. Offset voltage is specified worst case over a range of supply voltages, input voltage and temperature. It would
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LT1010
APPLICATIO S I FOR ATIO
be unrealistic to use these worst-case numbers above because paralleled units are operating under identical conditions. The offset voltage specified for VS = 15V, VIN = 0V and TA = 25C will suffice for a worst-case condition.
V+
IS A1 LT1010
IS VOUT
VIN
IOUT
A2 LT1010 IS - IOUT
1010 AI03
IS + IOUT
OUTPUT VOLTAGE (V)
V-
Output load current will be divided based on the output resistance of the individual buffers. Therefore, the available output current will not quite be doubled unless output resistances are matched. As for offset voltage, the 25C limits should be used for worst-case calculations. Parallel operation is not thermally unstable. Should one unit get hotter than its mates, its share of the output and its standby dissipation will decrease. As a practical matter, parallel connection needs only some increased attention to heat sinking. In some applications, a few ohms equalization resistance in each output may be wise. Only the most demanding applications should require matching, and then just of output resistance at 25C. Isolating Capacitive Loads The inverting amplifier below shows the recommended method of isolating capacitive loads. Noninverting amplifiers are handled similarly.
RS VIN CF 100pF A2 LT1010 CL
1010 AI04
RF 20k
-
A1 LT1007
+
U
At lower frequencies, the buffer is within the feedback loop so that its offset voltage and gain errors are negligible. At higher frequencies, feedback is through CF, so that phase shift from the load capacitance acting against the buffer output resistance does not cause loop instability. Stability depends upon the RFCF time constant or the closed-loop bandwidth. With an 80kHz bandwidth, ringing is negligible for CL = 0.068F and damps rapidly for CL = 0.33F. The pulse response is shown in the graph.
Pulse Response
CL = 0.068F 5 0 -5 CL = 0.33F 5 0 -5 0 50 100 TIME (s)
1010 AI05
W
UU
150
200
Small-signal bandwidth is reduced by CF, but considerable isolation can be obtained without reducing it below the power bandwidth. Often, a bandwidth reduction is desirable to filter high frequency noise or unwanted signals.
RF 2k CF 1nF A2 LT1010 CL
1010 AI06
-
RS 2k VIN A1 LT118A
VOUT
+
VOUT
The follower configuration is unique in that capacitive load isolation is obtained without a reduction in smallsignal bandwidth, although the output impedance of the buffer comes into play at high frequencies. The precision unity-gain buffer above has a 10MHz bandwidth without capacitive loading, yet it is stable for all load capacitance to over 0.3F, again determined by RFCF.
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9
LT1010
APPLICATIO S I FOR ATIO
This is a good example of how fast op amps can be made quite easy to use by employing an output buffer. Integrator A lowpass amplifier can be formed just by using large C F in the inverter described earlier, as long as the increasing closed-loop output impedance above the cutoff frequency is not a problem and the op amp is capable of supplying the required current at the summing junction.
CI IIN RF 20k
-
A1 LT1012 A2 LT1010 VOUT
1010 AI07
+
CF 500pF
If the integrating capacitor must be driven from the buffer output, the circuit above can be used to provide capacitive load isolation. As before, the stability with large capacitive loads is determined by RFCF. Wideband Amplifiers This simple circuit provides an adjustable gain video amplifier that will drive 1VP-P into 75. The differential pair provides gain with the LT1010 serving as an output
15V TYPICAL SPECIFICATIONS 1VP-P INTO 75 AT A = 2 0.5dB TO 10MHz 3dB DOWN AT 16MHz AT A = 10 0.5dB TO 4MHz -3dB = 8MHz OUTPUT (75)
8.2k
25 BIAS 22F 22F LT1010
+
+
-15V
PEAKING 5pF to 25pF
900
INPUT
Q1
Q2 Q1, Q2: 2N3866 5.1k 1k GAIN SET
+
0.01F 68F
-15V
1010 AI08
10
U
stage. Feedback is arranged in the conventional manner, although the 68F-0.01F combination limits DC gain to unity for all gain settings. For applications sensitive to NTSC requirements, dropping the 25 output stage bias value will aid performance.
R2 800 C1 15pF A2 LT1010 VOUT
1010 AI09
W
UU
-
A1 HA2625 VIN
+
R1 100
This shows the buffer being used with a wideband amplifier that is not unity-gain stable. In this case, C1 cannot be used to isolate large capacitive loads. Instead, it has an optimum value for a limited range of load capacitances. The buffer can cause stability problems in circuits like this. With the TO-220 packages, behavior can be improved by raising the quiescent current with a 20 resistor from the bias terminal to V +. Alternately, devices in the miniDIP can be operated in parallel. It is possible to improve capacitive load stability by operating the buffer class A at high frequencies. This is done by using quiescent current boost and bypassing the bias terminal to V - with more than 0.02F.
R2 1.6k
-
A1 HA2625 INPUT A2 LT1010 OUTPUT
1010 AI10
+
R1 400
Putting the buffer outside the feedback loop as shown here will give capacitive load isolation, with large output capacitors only reducing bandwidth. Buffer offset, referred to the op amp input, is divided by the gain. If the load resistance is known, gain error is determined by the output resistance tolerance. Distortion is low.
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LT1010
APPLICATIO S I FOR ATIO
R3 800 C1 20pF A2 LT1010
-
INPUT A1 HA2625
R4 39 OUTPUT 1
+
R1 50 R2 200 A3 LT1010
R5 39 OUTPUT 2
1010 AI11
OTHER SLAVES
The 50 video line splitter here puts feedback on one buffer with the others slaved. Offset and gain accuracy of slaves depend on their matching with master. When driving long cables, including a resistor in series with the output should be considered. Although it reduces gain, it does isolate the feedback amplifier from the effects of unterminated lines which present a resonant load. When working with wideband amplifiers, special attention should always be paid to supply bypassing, stray capacitance and keeping leads short. Direct grounding of test probes, rather than the usual ground lead, is absolutely necessary for reasonable results. The LT1010 has slew limitations that are not obvious from standard specifications. Negative slew is subject to glitching, but this can be minimized with quiescent
V+ R1 2k INPUT R3 20 A2 LT1010 C1 50pF C2 150pF R5 1k HOLD Q3 2N2907 R6 1k R2 2k D1 HP2810 R4 2k
+
A1 LT118A
-
A4 LT118A R8 5k C5 10pF R7 200k V- *2N2369 EMITTER BASE JUNCTION
Q2 2N2222
-
C4 1nF
+
U
current boost. The appearance is always worse with fast rise signal generators than in practical applications. Track and Hold The 5MHz track and hold shown here has a 400kHz power bandwidth driving 10V. A buffered input follower drives the hold capacitor, C4, through Q1, a low resistance FET switch. The positive hold command is supplied by TTL logic with Q3 level shifting to the switch driver, Q2. The output is buffered by A3. When the gate is driven to V - for HOLD, it pulls charge out of the hold capacitor. A compensating charge is put into the hold capacitor through C3. The step into hold is made independent of the input level with R7 and adjusted to zero with R10. Since internal dissipation can be quite high when driving fast signals into a capacitive load, using a buffer in a power package is recommended. Raising buffer quiescent current to 40mA with R3 improves frequency response. This circuit is equally useful as a fast acquisition sample and hold. An LT1056 might be used for A3 to reduce drift in hold because its lower slew rate is not usually a problem in this application. Current Sources A standard op amp voltage to current converter with a buffer to increase output current is shown here. As usual,
Q1 2N5432 SD C3 100pF
W
UU
-
A3 LT118A OUTPUT
+
D2* 6V
R9 10k R10 50k
1010 AI12
R11 6.2k
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11
LT1010
APPLICATIO S I FOR ATIO
excellent matching of the feedback resistors is required to get high output resistance. Output is bidirectional.
R1 100k 0.01% V1 R4 10 0.1% IOUT R2 100k 0.01% IOUT = R2(V2 - V1) R1R4
-
A1 LT1012 R3 100k 0.01% V2 R4 100k 0.01% A2 LT1010
A3 LT118A C2 10pF D2 1N457
+
1010 AI13
R1 2k
VV 1V/V
This circuit uses an instrumentation amplifier to eliminate the matched resistors. The input is not high impedance and must be driven from a low impedance source like an op amp. Reversal of output sense can be obtained by grounding Pin 7 of the LM163 and driving Pin 5.
enables the current regulator to get control of the output current from the buffer current limit within a microsecond for an instantaneous short. In the voltage regulation mode, A1 and A2 act as a fast voltage follower using the capacitive load isolation technique described earlier. Load transient recovery as well as capacitive load stability are determined by C1. Recovery from short circuit is clean. Bidirectional current limit can be obtained by adding another op amp connected as a complement to A3.
A2 LT1010
IOUT = R1 10 0.1%
VIN 10R1
VIN 6 A1 LM163 x10 5
Output resistances of several megohms can be obtained with both circuits. This is impressive considering the 150mA output capability. High frequency output characteristics will depend on the bandwidth and slew rate of the amplifiers. Both these circuits have an equivalent output capacitance of about 30nF. Voltage/Current Regulator This circuit regulates the output voltage at VV until the load current reaches a value programmed by VI. For heavier loads, it is a precision current regulator. With output currents below the current limit, the current regulator is disconnected from the loop by D1 with D2 keeping its output out of saturation. This output clamp
12
-
7
2
IOUT
Supply Splitter Dual supply op amps and comparators can be operated from a single supply by creating an artificial ground at half the supply voltage. The supply splitter shown here can source or sink 150mA. The output capacitor, C2, can be made as large as necessary to absorb current transients. An input capacitor is also used on the buffer to avoid high frequency instability that can be caused by high source impedance.
V+ R1 10k A1 LT1010 C1 1nF R2 10k C2 0.01F C3 0.1F V +/2
3
1010AI14
-
D1 1N457
+
+
-
U
C1 1nF A2 LT1010 R2 2k A1 LT118A R3 2 OUTPUT R4 2k 0.1% R5 2k 0.1% R6 99.8k 0.1% VI 10mA/V
1010 AI15
W
+
UU
R7 99.8k 0.1%
1010 AI16
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LT1010
APPLICATIO S I FOR ATIO
High Current Booster
The circuit below uses a discrete stage to get 3A output capacity. The configuration shown provides a clean, quick way to increase LT1010 output power. It is useful for high current loads such as linear actuator coils in disk drives. The 33 resistors sense the LT1010's supply current with the grounded 100 resistor supplying a load for the LT1010. The voltage drop across the 33 resistors biases Q1 and Q2. Another 100 value closes a local feedback loop, stabilizing the output stage. Feedback to the LT1056 control amplifier is via the 10k value. Q3 and Q4, sensing across the 0.18 units, furnish current limiting at about 3.3A.
15pF 10k 15V 0.18
Q2 2N2222 10M 100 -5V
10k 0.01F
6
A1 LTC1050 7
2000pF
5V
+
68pF 22F 33
Q3 2N3906
1k
10k INPUT
-
LT1056 LT1010 100
Q1 MJE2955 OUTPUT 100 Q2 MJE3055 1k
1010 AI17
signal. The amplified difference between these signals is used to set Q2's bias, and hence, Q1's channel current. This forces Q1's VGS to whatever voltage is required to match the circuit's input and output potentials. The 2000pF capacitor at A1 provides stable loop compensation. The RC network in A1's output prevents it from seeing high speed edges coupled through Q2's collector-base junction. A2's output is also fed back to the shield around Q1's gate lead, bootstrapping the circuit's effective input capacitance down to less than 1pF. Gain-Trimmable Wideband FET Amplifier A potential difficulty with the previous circuit is that the gain is not quite unity. The figure labeled A on the next page maintains high speed and low bias while achieving a true unity-gain transfer function. This circuit is somewhat similar except that the Q2-Q3 stage takes gain. A2 DC stabilizes the input-output path and A1 provides drive capability. Feedback is to Q2's emitter from A1's output. The 1k adjustment allows the gain to be precisely set to unity. With the LT1010, output stage slew and full power bandwidth (1VP-P) are 100V/s and 10MHz respectively. - 3dB bandwidth exceeds 35MHz. At A = 10 (e.g., 1k adjustment set at 50), full power bandwidth stays at 10MHz while the -3dB point falls to 22MHz. With the optional discrete stage, slew exceeds 1000V/s and full power bandwidth (1VP-P) is 18MHz. - 3dB bandwidth is 58MHz. At A = 10, full power is available to 10MHz, with the - 3dB point at 36MHz.
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+
33 -15V
Q4 2N3904 22F
0.18
HEAT SINK OUTPUT TRANSISTORS
Wideband FET Input Stabilized Buffer The figure below shows a highly stable unity-gain buffer with good speed and high input impedance. Q1 and Q2 constitute a simple, high speed FET input buffer. Q1 functions as a source follower with the Q2 current source load setting the drain-source channel current. The LT1010 buffer provides output drive capability for cables or whatever load is required. Normally, this open-loop configuration would be quite drifty because there is no DC feedback. The LTC(R)1050 contributes this function to stabilize the circuit. It does this by comparing the filtered circuit output to a similarly filtered version of the input
-
+
U
5V INPUT Q1 2N5486 A A2 LT1010 -5V 0.1F 4 3 B 10M OUTPUT 2 0.1F 1k
1010 AI18
W
+
UU
13
LT1010
APPLICATIO S I FOR ATIO
Figures A and B show response with both output stages. The LT1010 is used in Figure A (Trace A = input, Trace B = output). Figure B uses the discrete stage and is slightly faster. Either stage provides more than adequate performance for driving video cable or data converters and the LT1012 maintains DC stability under all conditions.
Gain-Trimmable Wideband FET Amplifier
15V
1k
INPUT
Q1 2N5486 Q2 2N3904 0.01F
10M
10k
2k
1k GAIN ADJ 300
50
5.6k
A1 LT1012 0.002F
(A)
A = 0.2V/DIV B = 0.2V/DIV
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10ns/DIV
Figure A. Waveforms Using LT1010
14
-
+
U
Thermal Considerations for the MiniDIP Package The miniDIP package requires special thermal considerations since it is not designed to dissipate much power. Be aware that for applications requiring large output currents, another package should be used.
10pF 470 Q3 2N3906 A A2 LT1010 B OUTPUT 3k 1k 2N3904 3 A 3k 10M 3 2N3906 3k 1k 0.1F -15V B 15V 0.1F -15V
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W
UU
(B)
A = 0.2V/DIV B = 0.2V/DIV
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10ns/DIV
Figure B. Waveforms Using Discrete Stage
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LT1010
APPLICATIO S I FOR ATIO
Typical thermal calculations for the miniDIP package are detailed in the following paragraphs. For 4.8mA supply current (typical at 50C, 30V supply voltage--see supply current graphs) to the LT1010 at 15V, PD = power dissipated in the part is equal to: (30V)(0.0048A) = 0.144W The rise in junction is then: (0.144W)(130C/W--This is JA for the N package) = 18.7C. This means that the junction temperature in 50C ambient air without driving any current into a load is: 18.7C + 50C = 68.7C Using the LT1010 to drive 8V DC into a 200 load using 15V power supplies dissipates PD in the LT1010 where:
PD =
(
V+
- VOUT VOUT
)( )
( =
RL 15V - 8 V 8 V 200
)( ) = 0.280W
This causes the LT1010 junction temperature to rise another (0.280W)(0.130C/W) = 36.4C. This heats the junction to 68.7C + 36.4C = 105.1C.
Caution: This exceeds the maximum operating temperature of the device.
An example of 1MHz operation further shows the limitations of the N (or miniDIP) package. For 15V operation: PD at IL = 0 at 1MHz* = (10mA)(30V) = 0.30W This power dissipation causes the junction to heat from 50C (ambient in this example) to 50C + (0.3W) (130C/W) = 89C. Driving 2VRMS of 1MHz signal into a 200 load causes an additional
2V PD = * 15 - 2 = 0.130W 200
(
)
U
to be dissipated, resulting in another (0.130W) (0.130C/W) = 16.9C rise in junction temperature to 89C + 16.9C = 105.9C.
W
UU
Caution: This exceeds the maximum operating temperature of the device.
Thermal Resistance of DFN Package For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. The following table lists thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with one ounce copper.
Table 1. DFN Measured Thermal Resistance
COPPER AREA TOPSIDE 2500 sq mm 1000 sq mm 225 sq mm 100 sq mm BACKSIDE 2500 sq mm 2500 sq mm 2500 sq mm 2500 sq mm BOARD AREA 2500 sq mm 2500 sq mm 2500 sq mm 2500 sq mm THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 40C/W 45C/W 50C/W 62C/W
For the DFN package, the thermal resistance junction-tocase (JC), measured at the exposed pad on the back of the die, is 16C/W. Continuous operation at the maximum supply voltage and maximum load current is not practical due to thermal limitations. Transient operation at the maximum supply is possible. The approximate thermal time constant for a 2500sq mm 3/32" FR-4 board with maximum topside and backside area for one ounce copper is 3 seconds. This time constant will increase as more thermal mass is added (i.e. vias, larger board, and other components). For an application with transient high power peaks, average power dissipation can be used for junction temperature calculations as long as the pulse period is significantly less than the thermal time constant of the device and board.
*See Supply Current vs Frequency graph.
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15
LT1010
SCHE ATIC DIAGRA W
R3 1k Q7 Q9
DEFI ITIO OF TER S
Output Offset Voltage: The output voltage measured with the input grounded (split supply operation). Input Bias Current: The current out of the input terminal. Large-Signal Voltage Gain: The ratio of the output voltage change to the input voltage change over the specified input voltage range.* Output Resistance: The ratio of the change in output voltage to the change in load current producing it.* Output Saturation Voltage: The voltage between the output and the supply rail at the limit of the output swing toward that rail. Saturation Offset Voltage: The output saturation voltage with no load. Saturation Resistance: The ratio of the change in output saturation voltage to the change in current producing it, going from no load to full load.* Slew Rate: The average time rate of change of output voltage over the specified output range with an input step between the specified limits. Bias Terminal Voltage: The voltage between the bias terminal and V +. Supply Current: The current at either supply terminal with no output loading.
*Pulse measurements (~1ms) as required to minimize thermal effects.
16
W
U
W
Q1
(Excluding protection circuits)
R6 15
V+ R7 300 R10 200 Q18 BIAS Q17 Q19 R11 200 Q20 Q21 Q12 R8 1k Q15 R12 3k R14 7 OUTPUT
Q11 R5 1.5k
Q5
R2 1k Q6 Q3
R4 1k
C1 30pF
Q8
Q2 Q4 R1 4k Q13
R13 200 Q22 R9 Q16 4k
1010 SD
Q10
Q14
INPUT V-
U
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LT1010
PACKAGE DESCRIPTIO
3.5 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5 0.38 0.10 8
PIN 1 TOP MARK (NOTE 6)
(DD) DFN 1203
0.200 REF
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE
U
DD Package 8-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 0.05 3.00 0.10 (4 SIDES) 1.65 0.10 (2 SIDES) 0.75 0.05 4 0.25 0.05 2.38 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD 1 0.50 BSC 0.00 - 0.05
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17
LT1010
PACKAGE DESCRIPTIO
.300 - .325 (7.620 - 8.255)
.008 - .015 (0.203 - 0.381)
(
+.035 .325 -.015 8.255 +0.889 -0.381
)
INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
NOTE: 1. DIMENSIONS ARE
18
U
N8 Package 8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
.400* (10.160) MAX 8 7 6 5 .255 .015* (6.477 0.381) 1 2 3 4 .130 .005 (3.302 0.127) .045 - .065 (1.143 - 1.651) .065 (1.651) TYP .120 (3.048) .020 MIN (0.508) MIN .018 .003 (0.457 0.076)
N8 1002
.100 (2.54) BSC
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LT1010
PACKAGE DESCRIPTIO U
T Package 5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)
.147 - .155 (3.734 - 3.937) DIA .230 - .270 (5.842 - 6.858) .460 - .500 (11.684 - 12.700) .570 - .620 (14.478 - 15.748) .330 - .370 (8.382 - 9.398) .700 - .728 (17.78 - 18.491) .620 (15.75) TYP .165 - .180 (4.191 - 4.572) .045 - .055 (1.143 - 1.397) SEATING PLANE .152 - .202 .260 - .320 (3.861 - 5.131) (6.60 - 8.13) .095 - .115 (2.413 - 2.921) .155 - .195* (3.937 - 4.953) .013 - .023 (0.330 - 0.584) BSC .067 (1.70) .028 - .038 (0.711 - 0.965) .135 - .165 (3.429 - 4.191) * MEASURED AT THE SEATING PLANE
T5 (TO-220) 0801
.390 - .415 (9.906 - 10.541)
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT1010 RELATED PARTS
PART NUMBER LT1206 LT1210 LT1795 LT1886 DESCRIPTION 250mA, 60MHz Current Feedback Amplifier 1.1A, 35MHz Current Feedback Amplifier Dual 500mA, 50MHz CFA Dual 700MHz, 200mA Op Amp COMMENTS 900V/s, Excellent Video Characteristics 900V/s Slew Rate, Stable with Large Capacitive Loads 500mA IOUT ADSL Driver DSL Driver
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20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT/LWI 0806 REV C * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 1991

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